1. Field of the Invention
This invention relates to the field of digital recording on optical recording media such as optical disks, to signal detection techniques for this digital recording, and to signal detection techniques for Pulse Width Modulation (PWM) optically recorded digital data.
2. Description of the Related Art
When data is recorded on optical recording media such as on optical recording disks using PWM recording techniques, the edges of the recorded data pits, or the edges of the recorded magnetic domains, can physically shift position, for example due to thermal blooming effects of the disks. This edge shift causes read detection errors due to incorrectly set signal detection thresholds. It is noted, however, that the detected negative and positive signal edges will shift generally the same physical amount when the detection threshold is incorrectly set.
PWM data recording is well known and comprises a recording method whereby a signal transition in a bit cell time interval comprises a selected one of a binary 1 or a binary 0, whereas the lack of a signal transition in a bit cell time interval comprises the other of the two possible binary states 0 and 1. Since a no signal transition state in a bit cell carries data information, it is necessary that a detection clock be provided to accurately define the detection bit cell intervals. This detection clock signal must be synchronized with the bit cell interval that was used when the signal was originally recorded, i.e. when the PWM data was originally written on the optical media.
Optical recording provides special problems relative to synchronizing this detection clock to the original writing clock. For example, the physical properties of conventional optical recording media provide that the information or data that is recorded on or into the media can change in physical size, be it movement of the leading and/or trailing edges of a pit that is formed into the media that cause light to be reflected to a data detector, or be it the physical size or length of a magnetic or an opto-magnetic property that is written into the media. As a result of this physical movement of recorded data on the optical media, use of the leading and/or trailing edges of the recorded data to generate a detection clock is complicated.
The present invention provides a data channel that operates to eliminate edge shift in the detection signal by employing a clock channel having two digital Phase Locked Loops (PLLs). An advantage of the invention is that its digital channel configuration can be easily implemented and controlled by the use of digital logic.
While the use of dual clock channels is known in optical devices, this use has been restricted to use in dual analog clock channels.
In addition, it is known that others have provided an adaptive signal detection thresholding feature in a digital channel. However, the art has not provided a dual digital phase locked loop channel for optical recording.
The following U.S. Patents are of general interest relative to the present invention.
U.S. Pat. No. 4,734,900 describes an optical recording apparatus wherein an unintended width variation in PLM data is eliminated by the use of a phase locked loop. The apparatus restores and clocks PWM data in a data channel during either writing or reading of the data. More specifically, the leading and trailing edges of PWM data are monitored to detect any variations in the expected pulse width. When a variation is detected, the pulse width is restored to the expected pulse width by operation of a phase locked loop.
In one embodiment of U.S. Pat. No. 4,734,900, a phase locked loop keeps the leading edge in proper phase with a data clock signal, and a width correction signal moves the trailing edge into proper phase relationship with the data clock signal.
In another embodiment of U.S. Pat. No. 4,734,900, a counter counts pulses of a clock between leading and trailing edges of signals that chronologically represent detected leading edges and trailing edges of pulses from PWM data. A count that is representative of the expected count is subtracted from the counter content, and a low pass filter and scaler operate to generate a signal that is a measure of width variation. This width variation signal is used to control a double phase locked loop arrangement in the form of two phase shifters; i.e., a minus phase shifter and a plus phase shifter. These two phase shifters then provide phase shifts for independent clocks in their loops. These clocks being used to detect the leading and trailing edges of pulses respectively.
U.S. Pat. No. 5,235,590 describes read out apparatus for use with magneto optic recording media. In its description of prior art U.S. Pat. No. 5,235,590 describes an arrangement wherein a first PLL generates a first clock signal that is synchronized to the leading edge of a read signal, and wherein a second PLL generates a second clock signal that is synchronized to the trailing edge of the read signal. By way of two data separators, a synthesizing device, and a decoder, a non return to zero code signal is generated from the read signal.
In a first embodiment of U.S. Pat. No. 5,235,590, an arrangement that includes a delay line operates to delay the leading edge of a read signal, and a synthesized signal is generated whose rising edge corresponds in time to the rising edge of the delayed leading edge signal, and whose falling edge corresponds in time to the trailing edge of original read signal.
In a second embodiment of U.S. Pat. No. 5,235,590, an arrangement that includes a read signal integrator operates to make a judgement as to the domain lengths that are being read. This judgement signal is then used to correct the edge positions which are obtained from the read signal.
In third, fourth and fifth embodiments of U.S. Pat. No. 5,235,590, two delay lines are provided. One delay line provides a fixed delay, whereas the second delay line provides a delay that is determined by integrating the read out signal. An edge detector responds to the read out signal and operates to apply a trailing edge detection signal to the fixed delay line, and to apply a leading edge detection signal to the variable delay line. The two outputs of the two delay lines are used to generate a digital read out signal whose leading edge is subject to a variable delay and whose trailing edge is subject to a fixed delay.
U.S. Pat. No. 5,309,418 makes use of a PLL in an optical disk track counting arrangement wherein a tracking error signal is applied to the PLL. This signal is compared to the signal that is generated by the PLL so as to synchronize the phase between these two signals. A counter counts the number of tracks based upon the synchronized PLL signal.
Japanese documents JO43664426 and J57203213 are of general interest in that they utilize leading and trailing edge detection and PLLs.
While the art as exemplified by the above noted U.S. patents has been generally satisfactory for its limited intended purposes, the need remains in the art for an optical recording signal detection channel that eliminates edge shift in its read signal by the use of a clock channel having two digital PLLs.